1. Field of the Invention
The invention relates to an electron beam exposure mask (hereinafter, referred to as exposure mask) for use in irradiating a wafer with an electron beam for cell projection, an electron beam exposure method using the same, a method of fabricating a semiconductor device, and an electron beam exposure apparatus. In particular, the invention relates to an electron beam exposure mask, an electron beam exposure method, a method of fabricating a semiconductor device, and an electron beam exposure apparatus for improved yield.
2. Description of the Related Art
Conventionally, techniques of variable shaping and partial cell projection have been used as lithographic technologies utilizing an electron beam. In the variable shaping, exposures of arbitrary rectangular pattern are performed through electron beam deflection. On the other hand, in the partial cell projection, repeated portions of desired pattern are exposed by using cell masks. In these techniques, stencil masks several dozen times as large as the wafer are used as the exposure masks. For example, the maximum exposure area on a wafer subjected to the pattern exposure is a square area having sides of the order of 5 μm in length. These techniques, however, have a problem of lower throughput. To solve this problem, a technique is recently proposed in which the beam diameter of the electron beam on the mask is increased to 1 mm or so, and a stencil mask or a membrane mask four times as large as the wafer is used as the exposure mask. In this technique, the maximum exposure area on a wafer is, for example, a square area having sides of 250 μm in length.
With the adoption of such techniques, there is proposed another technique, in which an exposure mask is formed as a plurality of defined masks corresponding to the entire pattern of the chip (device) to be formed on the wafer, and the defined masks are subjected to electron beam cell projections. Before that, the defined masks used to be formed for only those repeated portions.
In such an improved technique, pattern exposures onto a chip having sides of e.g. 20 mm are performed with the electron beam set at approximately 1 mm in beam diameter on the mask. Besides, the chip area is defined into an 80 by 80 matrix to obtain 6400 defined areas of square shape on the wafer. Each of the defined areas has sides of 250 μm in length, and is subjected to approximately ¼ demagnified projection.
Accordingly, 6400 defined masks each having sides approximately four times those of the defined areas, or of 1 mm, are formed and arranged to constitute an exposure mask. Then, the electron beam emitted from an electron source, having a beam diameter of approximately 1 mm is projected to one of the defined masks. Thereby, the electron beam past the defined mask is transcribed to the wafer, applying cell projection to the defined mask.
Subsequently, such cell projection is successively performed on all the defined masks so that the whole pattern in the exposure mask can be transcribed to the wafer to perform the exposure of the entire chip area.
FIG. 1A is a sectional view showing a conventional membrane mask. FIG. 1B is a sectional view showing a conventional stencil mask.
As shown in FIG. 1A, a conventional membrane mask 100 has an SiN (silicon nitride) substrate 101 of required thickness. A laminated thin film 102 of 30-50 nm in thickness, composed of W (tungsten) and Cr (chromium) films of required pattern is formed on the SiN substrate 101. On the surface of the SiN substrate 101 is integrally formed a reinforcing frame 103 of matrix form. The reinforcing frame 103 is made of Si, and has a thickness of the order of 750 μm. Each matrix area constitutes a defined mask.
On the other hand, as shown in FIG. 1B, a conventional stencil mask 200 has an Si substrate 201 of required thickness, etched or otherwise processed to form recesses 202 in a matrix arrangement. A thin portion 203 formed at the bottom of each recess 202 constitutes a defined mask. Each defined mask (thin portion) 203 has pattern openings 204 of predetermined configuration. The silicon substrate 201 forms frame portions 205 between the recesses 202.
Now, in the partial cell projection technique using the conventional exposure mask of a several dozen magnification, the stencil mask serving as the exposure mask uses an Si substrate having a thickness of the order of 10-20 μm. Meanwhile, the stencil mask to be used as the 4-time-exposure mask in the improved technique needs to form finer patterns, and therefore requires to be reduced to 2 μm or so in thickness with respect to the thickness of the Si substrate. The thinning lowers the mechanical strength of the stencil mask. Therefore, the possibility of mask defects in the mask fabrication rises to make a defect-free exposure mask difficult to fabricate.
Moreover, in the technique of using defined masks, the plurality of defined masks constituting a stencil mask require that not only the patterns for those repeated portions but also the entire chip pattern be defined into the split patterns having a plurality of different patterns. This means easier production of mask defects as compared to the case of fabricating the exposure mask of the order of a several dozen magnification for forming identical repeated patterns. As a result, it becomes difficult to form all the defined masks without any defect.
For such defective membrane mask and stencil mask, pattern repair technologies used for photomasks of optical exposure system are difficult to apply without loss of the function as an exposure mask. Such pattern repair technologies include a focused ion beam (FIB) method in which pattern repairs are carried out by focusing an ion beam onto a metal thin film, such as a chromium film, constituting the mask pattern. Accordingly, the defective exposure masks are unusable, and they require re-fabrication. This results in a problem that the exposure masks drop in production yield, and then rise in fabrication costs.